1. Field of the Invention
This invention relates generally to digital computer systems that employ high density memory devices having memory cells for storing signals therein, which signals may be read out in accordance with address signals applied thereto. More specifically, this invention is directed to a Y address decoder that is used to select a Y coordinate of an X-Y matrix memory cell array for evaluation of a memory cell located at the selected X and Y coordinates of such a memory array.
2. Description of the Prior Art
One example of the type of X-Y matrix array high density read only memory unit with which the present invention may be used, is disclosed in U.S. Pat. No. 3,728,696 issued to Polkinghorn on Apr. 17, 1973, also owned by the assignee of the present invention. The high density of that read-only memory unit is achieved by alternating bit lines and ground lines between cell locations. This concept results in a reduction in the number of diffusion regions from three for each two memory gates to two for each two memory gates. However, in such a high density ROM a particular combination of bit line and an adjacent ground line is selected to evaluate the logic state of each cell location. It is well known that in such memory units, the logic states are determined by whether or not a transistor stage is present at a selected cell location. Therefore, evaluation of a memory cell location is achieved by ascertaining whether or not current can be passed through the ground line and bit line that are adjacent to the selected cell location.
An X decoder is usually employed to enable a word line (row of cell locations) that include selected cell locations and a Y decoder is usually employed to enable the appropriate bit line and ground line combination for testing whether current can be passed through a column of cell locations that includes the selected cell location. However, since current can be conducted through only the enabled cells located at the intersection of the selected row and column, only those cell locations are subjected to the current passage test in response to a single set of address signals.
An optimum Y decoder should permit selection of the appropriate bit line and ground line combinations with (1) a minimum of selection logic, (2) a minimum number of series devices to which the evaluation current must pass before applied to an output driver, and (3) without requiring a reduction in the density of cells in the read-only memory unit.
Selection logic minimization is desirable to permit an entire set of memory devices (i.e. memory cell array, X decoder, and Y decoder) to be fabricated on a single integrated circuit chip of reasonable size. Minimization of the number of series devices through which evaluation current must pass is desirable to achieve short read-out time delays because each such device contributes to the time delay between the time of the addressing of a cell location and the time of the evaluation of a cell location. Obviating a reduction in memory cell density is clearly desirable to preclude nullification of the advantages otherwise obtained in achieving a high density memory cell configuration.
Known prior art Y decoders exclusively use either direct decode logic such as the logic described below in conjunction with prior art FIGS. 2, 4 and 7, or gating logic. Direct decode logic utilizes the signals of a binary coded selection address to control the conductivity of switches, such as field effect transistors, FETs, that are in the possible paths of the evaluation current of the selected cell locations. Although direct decode logic lends itself to a reduction in the selection logic required, it is disadvantageous from the standpoint of evaluation delay time because a larger number of series devices in the evaluation current path are employed to perform the selection process.
Gating-logic utilizes the signals of a binary coded selection address to generate a corresponding gating signal that is then applied to a single gating switch in the appropriate bit line and to a single gating switch in the appropriate ground line. Although gating-logic lends itself to a reduction in evaluation delay time, it is disadvantageous from the standpoint of the substantial increase in the selection logic required, or, in the alternative, from the standpoint of the decrease in memory cell density required to alleviate the increase in the required selection logic.